In ASIC (Application Specific Integrated Circuit) solutions and other types of integrated circuits especially for baseband and application processing in e.g. mobile phones, there are typically several units accessing memory, for example one or more CPUs, one or more DSPs, one or more communication links (wireless, UART, USB, etc.), and/or potentially also hardware accelerators for certain applications, routines, procedures, etc. Furthermore, the system normally has several instances and/or types of memory, which may comprise off-chip volatile, off-chip non-volatile, and different types of on-chip memory. These memories tend to be shared, completely or in part, by the various units that access memory. There is thus need for a memory controller that route memory accesses from and to the memory units and the units that access memory as efficiently as possible.
In most embedded systems, the memory controller is such that only one unit at a time is allowed to access any of the memories that are shared, i.e. a complete serialization of accesses to these memories. This is a low-complexity solution, where the accessing units might be sharing a single memory bus, and where the memories are all connected to this shared bus. The performance of such processing systems, on the other hand, is poor, and the impact when having real-time critical software can be devastating; either the real-time critical tasks get constant high priority access to the memories, which might result in ‘starvation’ of other tasks, and/or the system might show poor real-time characteristics.
In other solutions, a network of data links or buses is supported so that the unit's memory requests can be independently routed to their target memory, and memory conflicts appear only when more than one unit access the same physical memory module or memory bank that can be separately accessed. While such solutions provide much better performance, they have traditionally been considered significantly more complex; not only in terms of actual silicon area (which is becoming less significant), but also in terms of power consumption and engineering effort. The latter because most such solutions are uniquely designed for a specific system or implementation and are not designed to be scalable. Scalable in this context means that the same basic design and architecture can be used for both low-end, rather low-functionality, and small-area implementations as well as high-end, functionality-rich and performance demanding implementations.
Support for data transfer, such as DMA (Direct Memory Access), varies in complexity and functionality. Many present embedded systems has a simple DMA unit, that after setup by the CPU transfers a programmable amount of data from a programmable memory region to another programmable memory region. The transfer can be carried out without any intervention by a processor (except a programming/setup phase). If the data transfer occupies memories separate from the other accessing units and if the memory controller/network supports such parallel access, the data transfer will not cause any overhead. If accessing units target the same memory or memory bank as the DMA data transfer, there are typically two different schemes. Transparent DMA allows the DMA accesses to be carried out only when the memories are temporarily idle, on a granularity of individual accesses, while in non-transparent DMA much larger chunks of data are transferred which might lead to other units being locked out from the involved memories during a protracted consecutive period of time.
Some DMA controllers are more sophisticated, and support some number of virtual channels mapped on another number of physical channels in such a way that each physical channel defined by some interconnect capabilities can be programmed to take care of a number of different ongoing data channels. Each of these data channels can be either setup to transfer a given region of data from one memory to another, or be setup to move incoming data from a UART or USB interface buffer to other buffers dependent on signalling from the UART or USB where the buffer addresses are changed dynamically according to a predefined pattern (for example, double- or triple-buffering, each being filled in turn), etc. Such DMA controllers are often separate from the memory controller, although they have one or several data channels into it. Moreover, such DMA controllers are often rather complex circuits being designed to be inserted as a part of a design and are not scalable.
Many previous implementations of memory controllers as well as mechanisms that support data transfers exist. However, there are certain features not commonly found that are critical to upcoming architecture generations having a need for efficient, relatively low-complexity and/or scalable solutions.
First, since the solution must be scalable it must support a range of designs, and thereby it cannot be overly complex. At the same time, one requirement for performance as well as real-time issues is that different units shall be able to access different memories or memory banks independently without conflict. In addition, appropriate support for automatic data transfers is imperative, and because of the different characteristics of various software, it should be possible to be setup and act dynamically. The combined requirements of parallelism of independent accesses, dynamic support for automatic data transfers, scalability, and rather low complexity typically make the commonly known solutions inappropriate. While low-end implementations have few units accessing memory and rather low performance demands, their complexity must be kept rather low and the silicon area small. By contrast, a high-end implementation has demands on high-performance and more units accessing more memories or memory banks. Traditionally, this leads to completely different designs increasing the complexity of ASIC design, software design, test and verification.
U.S. Pat. No. 6,327,642 discloses a memory system comprising a main memory coupled to a plurality of parallel virtual access channels designed to improve memory access.
However, the use of cache in connection with access channels adds to the complexity of the design. Additionally, no support for DMA/data transfer between parts of the memory is given. Additionally, no support of pre-fetching, chaining or dynamic control giving flexibility is disclosed.
The object of the invention is to provide an electrical device for controlling memory access that is efficient, highly flexible and enables scalable implementation.
An additional object is to provide an electrical device for controlling memory access that enables a reduction of the risk of conflict with respect to memory access between memory accessing devices.